Various embodiments described herein relate to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices having a vertical channel transistor and methods of manufacturing the same.
To increase an integration density of semiconductor devices, a line width of patterns of semiconductor devices has been gradually reduced. A fine pattern formation technology for a next generation semiconductor device may be achieved by adopting a new and high cost exposure technology.
The integration density of semiconductor devices may also be increased by changing, for example, a structure of a field effect transistor (FET). For example, the semiconductor device may increase an integration density by adopting vertical field effect transistors having a different structure from planar type field effect transistors. A vertical field effect transistor may include a source region, a channel body and a drain region that are vertically stacked on a semiconductor substrate. Those vertical field effect transistors may be applied to various semiconductor devices, for example, memory devices.
In the case of adopting vertical field effect transistors to semiconductor devices, a drain region or source region of the vertical field effect transistor may be electrically connected to a conductive pattern. In this case, if the conductive pattern is misaligned with the source region or the drain region, the semiconductor device may incorrectly operate.